1. Field of the Invention
The present invention relates to a semiconductor apparatus with MOS transistors and a method for manufacturing the semiconductor apparatus, and, in particular, to a semiconductor apparatus having an n-channel MOS transistor and a p-channel MOS transistor in which two conductive types of gates are connected with each other and a method for manufacturing the semiconductor apparatus.
2. Description of the Related Art
A large scale integrated semiconductor apparatus has been recently manufactured to process a large number of pieces of data and instructions at a high speed. The apparatus is mainly composed of a large number of metal-oxide-semiconductor (MOS) transistors. Therefore, each of the MOS transistors has been miniaturized so that the gate length of the MOS transistors is lessened to 0.5 .mu.m or below.
In cases where miniaturized MOS transistors are fabricated to form the semiconductor apparatus, a so-called short channel effect is enhanced in each of the MOS transistors. Particularly, the short channel effect is remarkably enhanced in a buried channel type of MOS transistor in which a conducting channel is induced in a region far from a gate oxide film. Therefore, it is impossible to precisely control the amount of drain current transmitted through the conducting channel with gate charge applied to a gate electrode on the gate oxide film. In this case, the gate electrode is generally formed of pollcrystalline silicon because the polycrystalline silicon surpasses aluminium for electrode reliability.
To avoid the enhancement of the short channel effect, a surface channel type of MOS transistor in which a conducting channel is induced at a surface of a silicon substrate has been proposed. That is, the short channel effect is effectively reduced in the surface channel type of MOS transistor.
In addition, in cases where an enhancement type of MOS transistor is fabricated, the relation of work functions between the polycrystalline silicon used as the gate electrode and the silicon substrate must be considered. Therefore, as is well known, an n type polycrystalline silicon gate electrode is required in an n-channel enhancement type of MOS transistor, while a p type polycrystalline silicon gate electrode is required in a p-channel enhancement type of MOS transistor.
Therefore, in cases where a semiconductor apparatus such as a CMOS inverter in which two conductive types of gates are connected is manufactured, an n type polycrystalline silicon gate and a p type polycrystalline silicon gate are inevitably arranged on a semiconductor chip. In this case, the n and p type polycrystalline silicon gates are respectively fabricated by implanting impurities into an intrinsic polycrystalline silicon film by applying an ion implantation technique to achieve a prescribed concentration of the impurities more than a regular value (10.sup.19 cm.sup.-2), improved reproductivity of impurity profiles and low-temperature processing.
However, because the impurities are implanted into both the n type polycrystalline silicon gate and the p type polycrystalline silicon gate at a high dose before a heat treatment is performed to activate the n type impurities and the p type impurities, the concentration of the impurities implanted into the gates is considerably low as compared with that in the diffusion technique. Therefore, the resistance of both the n type polycrystalline silicon gate and the p type polycrystalline silicon gate becomes 10 or more times as large as that of the gates doped the impurities by applying the diffusion technique.
Therefore, a wiring structure composed of multi layers has been proposed to prevent the increase of the resistance in the polycrystalline silicon gates. In detail, the multi layers consist of a polycrystalline silicon layer and a metal layer deposited on the polycrystalline silicon layer. In this case, because the metal layer has a low resistance, the resistance of a gate electrode consisting of both the polycrystalline silicon layer and the metal layer is lowered.
However, the impurities are diffused into the metal layer at a high degree because diffusion coefficient for the impurities in metal is considerably high as compared with that for the impurities in the polycrystalline silicon gate. Therefore, the impurities implanted in one of the polycrystalline silicon gates are diffused into the other polycrystalline silicon gate through the metal layer even though a heat treatment is performed to the n type polycrystalline silicon gate to activate the impurities. As a result, work functions of the polycrystalline silicon gates are considerably varied.
Accordingly, there is a drawback that a threshold voltage V.sub.th and a transconductance g.sub.m of each of the polycrystalline silicon gates are considerably fluctuated. 2.1. Previously Proposed Art
The above drawback is solved in cases where the metal layers deposited on the polycrystalline silicon layers are separated from each other.
A conventional semiconductor apparatus with MOS transistors are described with reference to FIG. 1.
FIG. 1 is a sectional view structurally showing a conventional semiconductor apparatus laid open to public inspection under Japanese Patent Provisional Publication No. 203366/1991 (HEI 3-203366), both a gate region of an n channel MOS transistor and a gate region of a p channel MOS transistor being shown to indicate a boundary region between both gate regions.
As shown in FIG. 1, a conventional semiconductor apparatus 11 is provided with a p type silicon substrate 12 mounting both an n-channel MOS transistor and a p-channel MOS transistor, a p type well region 13 through which electrons are transmitted from a source to a drain in the n-channel MOS transistor, an n type well region 14 through which holes are transmitted from a source to a drain in the p-channel MOS transistor, field oxide layers 15 for separating the n-channel MOS transistor from the p-channel MOS transistor, a first gate oxide film 16 of the p-channel MOS transistor arranged between the field oxide layer 15 for electrically separating a channel in the well region 13 from a gate of the p-channel MOS transistor, a second gate oxide film 17 of the n-channel MOS transistor arranged between the field oxide layer 15 for electrically separating a channel in the well region 14 from a gate of the n-channel MOS transistor, an n type polycrystalline silicon film 18 deposited on the gate oxide film 16 and the field oxide layer 15, a p type polycrystalline silicon film 19 deposited on the gate oxide film 17 and the field oxide layer 15, a first titanium silicide film 20 deposited on the n type polycrystalline silicon film 18, a second titanium silicide film 21 deposited on the p type polycrystalline silicon film 19, a layer insulation film 22 deposited on the titanium silicide films 20, 21, and a metal wiring network 23 deposited on the titanium silicide films 20, 21 and the polycrystalline silicon films 18, 19 through a contact hole 24 opened in the layer insulation film 22.
The n type polycrystalline silicon film 18 is positioned in contact with the p type polycrystalline silicon film 19, while the titanium silicide film 20 is positioned away from the titanium silicide film 21. Therefore, the titanium silicide films 20, 21 and the polycrystalline silicon films 18, 19 are electrically connected with the metal wiring network 23 through the same contact hole 24.
In the above configuration of the conventional semiconductor apparatus 11, signals are transmitted to the polycrystalline silicon films 18, 19 through the metal wiring network 23 and the titanium silicide films 20, 21 to control the MOS transistors mounted on the silicon substrate 12. In this case, although impurities implanted in the polycrystalline silicon film 18 (19) can be diffused into titanium silicide film 20 (21) according to a high diffusion coefficient for the impurities in the titanium silicide films 20, 21, the impurities are not diffused from the silicon film 18 (or 19) to the other silicon film 19 (or 18) because the titanium silicide film 20 is positioned away from the titanium silicide film 21.
Therefore, the resistance of the polycrystalline silicon films 18, 19 is not increased. In addition, because the titanium silicide films 20, 21 with low resistivity are deposited on the polycrystalline silicon films 18, 19, the silicon films 18, 19 with comparatively high resistivity are formed thin. Therefore, the resistance of a gate electrode consisting of both the silicon film 18 and the titanium silicide film 20 is low. Also, the resistance of a gate electrode consisting of both the silicon film 19 and the titanium silicide film 21 is low.
Accordingly, the increase of the resistance of the silicon films 18, 19 is intended to be prevented so that the strength of the signals is not decreased. That is, the MOS transistors mounted on the silicon substrate 12 is intended to be reliably controlled.
However, a p-n junction is formed at a boundary surface between the n type polycrystalline silicon film 18 and the p type polycrystalline silicon film 19.
In this case, when either the n type polycrystalline silicon film 18 or the p type polycrystalline silicon film 19 is applied voltage through the metal wiring network 23, either forward voltage or reverse voltage is applied to the p-n junction. Therefore, either forward current or reverse current passes through the p-n junction so that signals transmitted to the films 18, 19 are not accurately controlled. As a result, there is a drawback that the possibility of faulty operation is increased in the semiconductor apparatus 11 in which two conductive types of films 18, 19 are connected.
In addition, because the n type polycrystalline silicon film 18 is positioned in contact with the p type polycrystalline silicon film 19, the impurities in one of the polycrystalline silicon films 18 (19) are necessarily diffused into the other polycrystalline silicon film 19 (18) although the diffusion length of the impurities in the polycrystalline silicon films 18, 19 is considerably smaller than that in the titanium silicide films 20, 21. For example, after a heat treatment is performed to the n type polycrystalline silicon film 18 at a temperature of 850.degree. C. for 30 minutes to bond the impurities such as arsenic atoms with silicon atoms, the arsenic atoms are diffused by 1 .mu.m or above.
Therefore, as shown in FIG. 2, the arsenic atoms implanted in the n type polycrystalline silicon film 18 are initially diffused into the p type polycrystalline silicon film 19, then the arsenic atoms are deeply diffused into the titanium silicide film 21. Thereafter, the arsenic atoms deeply diffused into the titanium silicide film 21 are again diffused into the p type polycrystalline silicon film 19. Therefore, the arsenic atoms are deeply diffused into the p type polycrystalline silicon film 19. Also, the impurities such as boron atoms implanted in the p type polycrystalline silicon film 19 are initially diffused into the n type polycrystalline silicon film 18, then the boron atoms are deeply diffused into the titanium silicide film 20. Thereafter, the boron atoms deeply diffused into the titanium silicide film 20 are again diffused into the n type polycrystalline silicon film 18. Therefore, the boron atoms are deeply diffused into the n type polycrystalline silicon film 18.
Accordingly, there is a drawback that the strength of signals transmitted to the films 18, 19 are decreased to increase the possibility of faulty operation.
The adverse influence exerted by the diffusion of the impurities is quantitatively examined by Inventors.
FIG. 3 quantitatively shows the variation of subthreshold characteristics in the n-channel transistor of the semiconductor apparatus 11 shown in FIG. 1 in cases where the distance L1 between the p type polycrystalline silicon film 19 and an active region of the n-channel MOS transistor ranges from 1 .mu.m to 4 .mu.m. The active region of the n-channel MOS transistor is just above the first gate oxide film 16.
As shown in FIG. 3, drain current is exponentially increased in proportion to gate voltage at a so-called subthreshold region. These phenomena are called subthreshold characteristics, In cases where the distance L1 between the p type polycrystalline silicon film 19 and the active region of the n-channel MOS transistor is 3 .mu.m or above, the subthreshold characteristics of the n-channel transistor are independent of the distance L1. However, in cases where the distance L1 is 2 .mu.m or below, the subthreshold characteristics of the n-channel transistor are dependent on the distance L1. That is, as the distance L1 is decreased, the gate voltage is decreased to get a prescribed drain current.
Therefore, the distance L2 between a contact surface of the polycrystalline silicon films 18, 19 and the titanium silicide film 20, or 21 must be above 1 .mu.m. In other words, the distance L3 between the titanium silicide films 20, 21 must be above 2 .mu.m. That is, the distance between the n type MOS transistor and the P type MOS transistor in the semiconductor apparatus 11 must be necessarily above 4 .mu.m in consideration of a marginal space required to put the wiring network 23 on the titanium silicide films 20, 21.
Accordingly, there is another drawback that the semiconductor apparatus 11 cannot be effectively miniaturized.
In addition, a process for patterning the titanium silicide films 20, 21 is additionally required because the process must be performed independent of other processes. Therefore, an additional photo mask is required to manufacture the semiconductor apparatus 11.
Accordingly, there is an additional drawback that the number of the processes to manufacture the semiconductor apparatus 11 is increased.
2.2 Improved-type of Previously Proposed Art
The above drawbacks are solved in cases where a gate electrode consisting of a polycrystalline silicon film and a metal layer is separated from another gate electrode consisting of another polycrystalline silicon film and another metal layer.
FIG. 4 is a sectional view structurally showing a conventional semiconductor apparatus laid open to public inspection under Japanese Patent Provisional Publication No. 169022/1991 (HEI 3-169022), both a gate region of an n channel MOS transistor and a gate region of a p channel MOS transistor being shown to indicate a boundary region between both gate regions.
As shown in FIG. 4, a conventional semiconductor apparatus 31 is provided with the p type silicon substrate 12, the p type well region 13, the n type well region 14, the field oxide layer 15, the first and second gate oxide films 16, 17 in the same manner as the semiconductor apparatus 11.
In addition, the semiconductor apparatus 31 is further provided with an n type polycrystalline silicon film 32 deposited on the gate oxide film 16 and the field oxide layers 15 for receiving a signal to control the electrons transmitted in the p type well region 13, a p type polycrystalline silicon film 33 deposited on the gate oxide film 17 and the field oxide layer 15 for receiving a signal to control the holes transmitted in the n type well region 14, a tungsten silicide film 34 deposited on the n type polycrystalline silicon film 32, a tungsten silicide film 35 deposited on the p type polycrystalline silicon film 33, a layer insulation film 36 for insulating the polycrystalline silicon films 32, 33 from polycrystalline silicon films (not shown) of other MOS transistors (not shown) mounted on the silicon substrate 12, and a metal wiring network 37 deposited on the tungsten silicide films 34, 35 through contact holes 38 opened in the layer insulation film 36.
The n type polycrystalline silicon film 32 is positioned away from the p type polycrystalline silicon film 33 through the layer insulation film 36.
In the above configuration of the conventional semiconductor apparatus 31, signals are transmitted to the polycrystalline silicon films 32, 33 through the metal wiring network 37 and the tungsten silicide films 34, 35 to control the MOS transistors mounted on the silicon substrate 12. In this case, because the n type polycrystalline silicon film 32 is positioned away from the p type polycrystalline silicon film 33, impurities implanted in the silicon film 32 (or 33) are not diffused into the other silicon film 33 (or 32). Accordingly, the strength of the signals transmitted to the gate electrodes is not decreased so that the MOS transistors mounted on the silicon substrate 12 can be reliably controlled.
2--2 Problems to be Solved by the Invention
However, the semiconductor apparatus 31 with the MOS transistors requires a plurality of contact holes 38 to transmit the signals to the polycrystalline silicon films 32, 33 because the n type polycrystalline silicon film 32 is positioned away from the p type polycrystalline silicon film 33. That is, as shown in FIG. 4, two contact holes 38 are required in the apparatus 31 with MOS transistors, while the single contact hole 24 is required in cases where the n type polycrystalline silicon film 18 is positioned in contact with the p type polycrystalline silicon film 19 in the semiconductor apparatus 11 shown in FIG. 1. Therefore, a space for arranging the added contact hole is additionally required with a marginal space. In addition, another space for separating the contact holes from each other is additionally required with another marginal space.
FIG. 5 is a plan view of the contact holes 38 in the conventional semiconductor apparatus 31 shown in FIG. 4 numerically showing a space required for the arrangement of the contact holes 38.
As shown in FIG. 5, in cases where each of the contact holes 38 is 0.6 .mu.m in diameter, the distance S1 between the polycrystalline silicon films 32, 33 is 0.5 .mu.m, the marginal space S2 between the polycrystalline silicon film 32 (33) and the contact hole 38 is 0.3 .mu.m, and the space S3 between the polycrystalline silicon film 32 (33) and the active region positioned just above the gate oxide film 16 (17) is 0.3 .mu.m, the distance S4 between the active regions of the MOS transistors is a minimum of 3.5 .mu.m.
Therefore, the distance between the MOS transistors is prolonged by the added contact hole 38.
Accordingly, there is a drawback that the semiconductor apparatus 31 cannot be effectively miniaturized.
In addition, because the area of the gate electrode consisting of both the silicon film 32 (33) and the tungsten silicide film 34 (35) is enlarged on the field oxide layer 15, parasitic capacity generated in the gate electrode is increased.
Accordingly, there is another drawback that the time-lag of the signals transmitted to the gate electrodes is considerably increased. That is, the semiconductor apparatus 31 with the MOS transistors cannot be accurately controlled.